1. Field of the Invention:
This invention generally relates to layout of integrated circuits (ICs), and more particularly to a configuration of bondpads used to connect an integrated circuit die to a first level package.
2. Description of the Related Art:
An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible.
In this disclosure, "n" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic, which introduce negatively charged majority carriers into the silicon, and "p" denotes silicon doped with atoms having less than four valence electrons (group III or lower), such as boron or phosphorus, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. A plus or minus superscript on an n or p indicates heavy or light doping, respectively. "Poly" denotes polycrystalline silicon, which is often used for resistor fabrication. Geometries and doping directly affect poly resistivity.
Integrated semiconductor devices are typically constructed en masse on a wafer of silicon or gallium arsenide. Each device generally takes the form of an integrated circuit (IC) die, which is attached to a leadframe with gold wires. The die and leadframe are then encapsulated in a plastic or ceramic package, which is then recognizable as an IC (integrated circuit). ICs come in a variety of forms such as dynamic random access memories (DRAMs), static random access memories (SRAMs), read only memories (ROMs), gate arrays, and so forth. The ICs are interconnected in myriad combinations on printed circuit boards by a number of techniques, such as socketing and soldering.
This invention relates to connection circuitry for connecting the circuits which are on the IC die to external circuits, as through a leadframe.
The attachment of the die to the leadframe with the gold wires is referred to as wirebonding. Wirebonding consists of using heat and pressure, along with ultrasonic energy to fuse the gold wire to an attachment point on the die, known as a die pad. In a typical process, the leadframe with a die mounted to it is heated to 230.degree., and ultrasonic energy in the range of 40-74 mW @ 60 KHz is applied. The ultrasonic energy is sufficient to break through an oxide coating on aluminum diepads on the wafer in order that the gold wires may bond to the diepads. The result is a fusion bond.
Semiconductor packaging has been referred to in terms of "levels" of packaging. The chip capsule generally constitutes a first level of packaging. A second level would then be a "card" or a printed circuit board. A fourth level may follow the third level.
Such semiconductor devices typically take the form of a semiconductor die. The die is generally electrically attached to a leadframe within a package. The leadframe physically supports the die and provides electrical connections between the die and the outside world.
As illustrated in FIG. 1, a typical IC input includes a wirebond pad or die pad. The pad rests on a layer of silicon dioxide ("oxide") or polysilicon ("poly") which prevents short circuiting to substrate if the pad is punctured during wafer sort or assembly. The die is generally electrically attached (wirebonded) to the leadframe by means of fine gold wires which are wirebonded to the pads. These fine gold wires function to connect the die pads to the leadframe, so that the gold wires are electrically in series with the leadframe leads. The leadframe and die is then encapsulated, in the form of the familiar integrated circuit. The packaged chip is then able to be installed on a circuit board by any number of techniques, such as socketing and soldering.
TAB bonding uses similar pads, although material may be added to the pads to enhance bonding integrity. The pads on TAB circuits are referred to as "bumps" because of the additional material. This TAB technology is known to those skilled in the art of semiconductor assembly. Other technologies exist, in which pads or bumps are used to attach a semiconductor die to a first level package. In any case, the die attach or wirebonding process is complicated, in that each external connection lead must be attached to the die, usually either by pressure, pressure bonding or thermal bonding techniques.
The above technologies utilize connection points (such as the bondpads) which are on the horizontal surface of the semiconductor. The connection point occupies substantial "real estate" (surface area) on the chip which could otherwise be used for circuitry. The use edge surfaces of the die are not used for such connections.
The space between adjacent dice on a semiconductor wafer is variously called the street, saw alley, scribe lane, separation area and space between the dice. The street is provided as space for a die saw to cut the wafer into individual (singulated) dice. Generally, circuitry on the die must terminate before the street in order that the circuitry not short or leak current to substrate after the die is cut.
The tendency for circuitry which extends into the location of the die saw cut to leak current has meant that circuitry had to terminate before the street. It would be desireable to be able to extend some circuitry into the street area. Of particular interest is the die bond locations (die pads), which have areas which are large enough to be seen by the naked eye.
If the edge of the die can be used for external connections, then the required real estate for the die bond locations could be reduced.
It is possible to vertically mount multiple dice onto a single horizontal supporting substrate, otherwise called a chipmount or motherdie. In that arrangement, the multiple dice could be connected to the supporting substrate or as daughter dice, much as daughter boards on an electronic device may be connected to a motherboard.
By placing the die bond locations at the edge of the die or near the edge of the edge of the die, the die can be attached by direct contact with the edge of the die. If a daughter die is vertically mounted to a mother die or mounting substrate, then the die bond locations can coincide with the mounting location of the daughter die to the mother die or mounting substrate.